View 74LVC4066_4115035.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

74LVC4066
Quad bilateral switch
Rev. 02 -- 27 August 2007 Product data sheet
1. General description
The 74LVC4066 is a high-speed Si-gate CMOS device. The 74LVC4066 provides four single pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V s Very low ON resistance: x 7.5 (typical) at VCC = 2.7 V x 6.5 (typical) at VCC = 3.3 V x 6 (typical) at VCC = 5 V s Switch current capability of 32 mA s High noise immunity s CMOS low-power consumption s Direct interface TTL-levels s Latch-up performance exceeds 250 mA s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Enable inputs accept voltages up to 5 V s Multiple package options s Specified from -40 C to +85 C and -40 C to +125 C
NXP Semiconductors
74LVC4066
Quad bilateral switch
3. Ordering information
Table 1. Ordering information Package Temperature range 74LVC4066D 74LVC4066PW 74LVC4066BQ -40 C to +125 C -40 C to +125 C -40 C to +125 C Name SO14 TSSOP14 DHVQFN14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin small outline package; 14 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 Type number
4. Functional diagram
1 13 4 5 8 6 11 12
1Y 1E 2Y 2E 3Y 3E 4Y 4E
1Z
2 1 2
1 13 # 4 3 # 9 # 10 8 6 11 12 # (a) # 5 #
1 X1 1 X1 1 X1 1 X1 (b)
1
2
2Z
3
13 # 4 5
1
3
3Z
9
8 6
1
9
4Z 10
11 12 #
1
10
mnb111
mnb112
Fig 1. Logic symbol
Fig 2. Logic symbol (IEEE/IEC)
Z
Y E
VCC
mna658
Fig 3. Logic diagram (one switch)
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
2 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
5. Pinning information
5.1 Pinning
terminal 1 index area 1Z 2Z 2Y 2E 2E 3E GND 5 6 7
001aad117
1Y 1Z 2Z 2Y
1 2 3 4
14 VCC 13 1E 12 4E
2 3 4 5 6 7 GND 3Y 8
14 VCC 13 1E 12 4E 11 4Y 10 4Z 9 3Z
4066
11 4Y 10 4Z 9 8 3Z 3Y
GND(1)
3E
1
1Y
4066
001aad118
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 4. Pin configuration for SO14 and TSSOP14
Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2. Symbol 1Y 1Z 2Z 2Y 2E 3E GND 3Y 3Z 4Z 4Y 4E 1E VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description independent input/output independent output/input independent output/input independent input/output enable input (active HIGH) enable input (active HIGH) ground (0 V) independent input/output independent output/input independent output/input independent input/output enable input (active HIGH) enable input (active HIGH) supply voltage
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
3 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
6. Functional description
Table 3. Input nE L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table[1] Switch OFF ON
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK ISK VSW ISW ICC IGND Tstg Ptot
[1] [2] [3]
Parameter supply voltage input voltage input clamping current switch clamping current switch voltage switch current supply current ground current storage temperature total power dissipation
Conditions
[1]
Min -0.5 -0.5 -50 [2]
Max +6.5 +6.5 50 +6.5 50 100 +150 500
Unit V V mA mA V mA mA mA C mW
VI < -0.5 V or VI < VCC + 0.5 V VI < -0.5 V or VI < VCC + 0.5 V enable and disable mode -0.5 < VSW < VCC + 0.5 V
-0.5 -100 -65
Tamb = -40 C to +125 C
[3]
-
The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. For SO14 packages: above 70 C derate linearly with 8 mW/K. For (T)SSOP14 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
4 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
8. Recommended operating conditions
Table 5. Symbol VCC VI VSW Tamb t/V Recommended operating conditions Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V
[1]
[2] [2] [1]
Conditions
Min 1.65 0 0 -40 -
Typ -
Max 5.5 5.5 VCC +125 20 10
Unit V V V C ns/V ns/V
To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no limit for the voltage drop across the switch. Applies to control signal levels.
[2]
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V II IS(OFF) input leakage current OFF-state leakage current ON-state leakage current pin nE; VCC = 5.5 V; VI = 5.5 V or GND VI = VIH or VIL; VCC = 5.5 V; see Figure 6 VI = VIH or VIL; VCC = 5.5 V; see Figure 7
[2]
-40 C to +85 C Min 0.65VCC 1.7 2.0 0.7VCC Typ[1] 0.1 0.1 Max 0.35VCC 0.7 0.8 0.3VCC 5 5
-40 C to +125 C Unit Min 0.65VCC 1.7 2.0 0.7VCC Max 0.7 0.8 0.3VCC 20 20 V V V V V V V A A
0.35VCC V
[2]
IS(ON)
[2]
-
0.1
5
-
20
A
ICC ICC
supply current VI = VCC or GND; VSW = GND or VCC; VCC = 5.5 V; IO = 0 A; additional pin nE; VI = VCC - 0.6 V; VCC = 5.5 V; supply current VSW = GND or VCC
[2]
-
0.1 5
10 500
-
40 5000
A A
[2]
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
5 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
Table 6. Static characteristics ...continued At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter CI CS(OFF) CS(ON) input capacitance OFF-state capacitance ON-state capacitance Conditions -40 C to +85 C Min Typ[1] 12.5 8.0 14.0 Max -40 C to +125 C Unit Min Max pF pF pF
[1] [2]
All typical values are measured at Tamb = 25 C. These typical values are measured at VCC = 3.3 V.
9.1 Test circuits
VCC VIL IS
VI
VCC VIH Z IS
VO VI
E Y GND
E Z GND Y
IS
VO
001aag488
001aag489
VI = VCC or GND and VO = GND or VCC.
VI = VCC or GND and VO = open circuit.
Fig 6. Test circuit for measuring OFF-state leakage current
Fig 7. Test circuit for measuring ON-state leakage current
9.2 ON resistance
Table 7. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(peak) Parameter Conditions -40 C to +85 C Min ON resistance (peak) VI = GND to VCC; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V 34.0 12.0 10.4 7.8 6.2 130 30 25 20 15 195 45 38 30 23 Typ[1] Max -40 C to +125 C Unit Min Max
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
6 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
Table 7. ON resistance ...continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(rail) Parameter ON resistance (rail) Conditions VI = GND; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V VI = VCC; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) VI = GND to VCC ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] [2] Typical values are measured at Tamb = 25 C and nominal VCC. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature.
[2]
-40 C to +85 C Min Typ[1] 8.2 7.1 6.9 6.5 5.8 10.4 7.6 7.0 6.1 4.9 26.0 5.0 3.5 2.0 1.5 Max 18 16 14 12 10 30 20 18 15 10 -
-40 C to +125 C Unit Min Max 27 24 21 18 15 45 30 27 23 15
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
7 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
9.3 ON resistance test circuit and graphs
40 RON () 30 VSW VCC VIH E Y GND Z 10
(4) VI ISW (5)
mna673
(1)
20
(2) (3)
0 0
001aag490
1
2
3
4 VI (V)
5
RON = VSW / ISW.
(1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V.
Fig 8. Test circuit for measuring ON resistance
Fig 9. Typical ON resistance as a function of input voltage; Tamb = 25 C
55 RON () 45
001aaa712
15 RON () 13
001aaa708
35
(4) (3) (2) (1)
11
(1) (2)
25
9
(3) (4)
15
7
5 0 0.4 0.8 1.2 1.6 VI (V) 2.0
5 0 0.5 1.0 1.5 2.0 VI (V) 2.5
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 10. ON resistance as a function of input voltage; VCC = 1.8 V
Fig 11. ON resistance as a function of input voltage; VCC = 2.5 V
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
8 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
13 RON () 11
001aaa709
10 RON () 8
001aaa710
(1)
(1) (2)
9
(2) (3)
6
(3)
7
(4) (4)
5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V)
4 0 1 2 3 VI (V) 4
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 12. ON resistance as a function of input voltage; VCC = 2.7 V
Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V
7 RON () 6
001aaa711
5
(1) (2)
4
(3)
(4)
3 0 1 2 3 4 VI (V) 5
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 14. ON resistance as a function of input voltage; VCC = 5.0 V
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
9 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
10. Dynamic characteristics
Table 8. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit Figure 17. Symbol Parameter tpd Conditions
[2][3]
-40 C to +85 C Min Typ[1] Max
-40 C to +125 C Unit Min Max
propagation delay nY to nZ or nZ to nY; see Figure 15 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[4]
0.8 0.4 0.4 0.3 0.2 5.3 3.0 2.6 2.5 1.9 4.2 2.4 3.6 3.4 2.5
2.0 1.2 1.0 0.8 0.6 10 5.6 5.0 4.4 3.9 9.0 5.5 6.5 6.0 5.0
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
3.0 2.0 1.5 1.5 1.0 12.5 7.0 6.5 5.5 5.0 11.5 7.0 8.5 7.5 6.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ten
enable time
nE to nY or nZ; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
1.0 1.0 1.0 1.0 1.0
[5]
tdis
disable time
nE to nY or nZ; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
1.0 1.0 1.0 1.0 1.0
[6]
CPD
power dissipation capacitance
CL = 50 pF; fi = 10 MHz; VI = GND to VCC VCC = 2.5 V VCC = 3.3 V VCC = 5.0 V
-
11.0 12.5 15.6
-
-
-
pF pF pF
[1] [2] [3] [4] [5] [6]
Typical values are measured at Tamb = 25 C and nominal VCC. tpd is the same as tPLH and tPHL. Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + {(CL + CS(ON)) x VCC2 x fo} where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CS(ON) = maximum ON-state switch capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; {(CL + CS(ON)) x VCC2 x fo} = sum of the outputs.
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
10 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
10.1 Waveforms and test circuit
VI nY or nZ input GND t PLH VOH nZ or nY output VOL
001aaa541
VM
VM
t PHL
VM
VM
Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. Input (nY or nZ) to output (nZ or nY) propagation delays
VI nE input GND t PLZ VCC nY or nZ output LOW-to-OFF OFF-to-LOW VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH Vy VM GND switch enabled switch disabled switch enabled
001aaa542
VM
t PZL
VM VX t PZH
nY or nZ
Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times Table 9. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5 VCC 0.5VCC 1.5 V 1.5 V 0.5VCC VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.15 V VOH - 0.15 V VOH - 0.3 V VOH - 0.3 V VOH - 0.3 V
Supply voltage
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
11 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times.
Fig 17. Load circuit for switching times Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2VCC 2VCC 6V 6V 2VCC
Supply voltage
10.2 Additional dynamic characteristics
Table 11. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol THD Parameter total harmonic distortion Conditions RL = 10 k; CL = 50 pF; fi = 1 kHz; see Figure 18 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V RL = 10 k; CL = 50 pF; fi = 10 kHz; see Figure 18 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V 0.068 0.009 0.008 0.006 % % % % 0.032 0.008 0.006 0.005 % % % % Min Typ Max Unit
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
12 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
Table 11. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol f(-3dB) Parameter -3 dB frequency response Conditions RL = 600 ; CL = 50 pF; see Figure 19 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V RL = 50 ; CL = 5 pF; see Figure 19 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V iso isolation (OFF-state) RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V RL = 50 ; CL = 5 pF; fi = 1 MHz; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V Vct crosstalk voltage between digital inputs and switch; RL = 600 ; CL = 50 pF; fi = 1 MHz; tr = tf = 2 ns; see Figure 21 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V Xtalk crosstalk between switches; RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 22 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V between switches; RL = 50 ; CL = 5 pF; fi = 1 MHz; see Figure 22 VCC = 1.65 V VCC = 2.3 V VCC = 3 V VCC = 4.5 V
74LVC4066_2
Min
Typ
Max
Unit
-
170 210 212 215 > 500 > 500 > 500 > 500
-
MHz MHz MHz MHz MHz MHz MHz MHz
-
-46 -46 -46 -46
-
dB dB dB dB
-
-42 -42 -42 -42
-
dB dB dB dB
-
69 87 156 302
-
mV mV mV mV
-
-58 -58 -58 -58
-
dB dB dB dB
-
-58 -58 -58 -58
-
dB dB dB dB
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
13 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
Table 11. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Qinj Parameter charge injection Conditions CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Figure 23 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 4.5 V VCC = 5.5 V 3.3 4.1 5.0 6.4 7.5 pC pC pC pC pC Min Typ Max Unit
10.2.1 Test circuits
VCC VIH E Y/Z
600
0.5VCC
RL
Z/Y
10 pF
VO
CL
fi
D
001aag492
Test conditions: VCC = 1.65 V: Vi = 1.4 V (p-p). VCC = 2.3 V: Vi = 2 V (p-p). VCC = 3 V: Vi = 2.5 V (p-p). VCC = 4.5 V: Vi = 4 V (p-p).
Fig 18. Test circuit for measuring total harmonic distortion
VCC VIH
0.1 pF
0.5VCC
RL
E Y/Z Z/Y
VO
CL
fi
50
dB
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads -3 dB.
Fig 19. Test circuit for measuring the frequency response when switch is in ON-state
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
14 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
0.5VCC
RL VIL 0.1 pF
VCC E Z/Y
0.5VCC
RL
Y/Z
VO
CL
fi
50
dB
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF-state)
VCC E Y/Z G
logic input
Z/Y
VO
RL CL
50
600
0.5VCC
0.5VCC
001aag494
Fig 21. Test circuit for measuring crosstalk voltage (between digital inputs and switch)
0.5VCC VIH
0.1 pF Ri 600 fi 50
1E 1Y or 1Z CHANNEL ON 1Z or 1Y
RL
CL 50 pF
VO1
0.5VCC VIL 2E 2Y or 2Z
Ri 600 RL
2Z or 2Y CHANNEL OFF
CL 50 pF
VO2
001aag496
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 22. Test circuit for measuring crosstalk between switches
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
15 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
VCC E
Rgen
Y/Z
Z/Y
RL 1 M CL 0.1 nF
VO
G
logic input
Vgen
001aag495
logic input (E)
off
on
off
VO
VO
mna675
Qinj = VO x CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
16 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 pin 1 index Lp 1 e bp 7 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 24. Package outline SOT108-1 (SO14)
74LVC4066_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
17 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 25. Package outline SOT402-1 (TSSOP14)
74LVC4066_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
18 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 6 vMCAB wM C y1 C
C y
1 Eh 14
7 e 8
13 Dh 0
9 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 26. Package outline SOT762-1 (DHVQFN14)
74LVC4066_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
19 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
12. Abbreviations
Table 12. Acronym CMOS TTL HBM ESD MM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Device Under Test
13. Revision history
Table 13. Revision history Release date 20070827 Data sheet status Product data sheet Change notice Supersedes 74LVC4066_1 Document ID 74LVC4066_2 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 2 "Features": Added: Wide supply voltage range from 1.65 V to 5.5 V Added: Switch handling capability of 32 mA Added: Multiple package options Deleted: Complies with JEDESD-8 standards Added: Specified from -40 C to +85 C and -40 C to +125 C Added: Enable input accepts voltages up to 5 V
* * *
74LVC4066_1
Section 7 "Limiting values" Added: Derating factors of the applicable packages Section 9 "Static characteristics" Changed: Maximum values of ON resistance (peak) parameters and graphics. Section 10 "Dynamic characteristics": Changed: Typical values of the charge injection. Product specification -
20030812
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
20 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC4066_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 27 August 2007
21 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
16. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 9.1 9.2 9.3 10 10.1 10.2 10.2.1 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuit . . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . . 12 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 August 2007 Document identifier: 74LVC4066_2

▲Up To Search▲

Price & Availability of 74LVC4066

	To Download 74LVC4066 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .